Many conventional semiconductor device fabrication processes produce semiconductor devices that exhibit short channel effects. Consequently, the development of processes that yield devices where the short channel effect is controlled in the devices that are produced is one of the biggest challenges confronting device manufacturers. The primary impact of the short channel effect is to cause an increase in the leakage or “off” current that is exhibited by a device when the device is in the off state. This leakage impacts the capacity of the device to perform ideally as a switch. A conventional process that illustrates this problem is shown in FIGS. 1A–1F.
FIG. 1A shows a diagram of a semiconductor wafer that is patterned using a conventional fabrication process. The diagram shows polycrystalline gate structures 101A–101D, source regions 103A and 103B, drain regions 105A and 105B, and shallow trench isolation (STI) regions 107A and 107B. An illustration that depicts a perspective view of the wafer as seen when cut along lines BB″ (see FIG. 1A) is shown in FIG. 1B. An illustration that depicts a perspective view of the wafer as seen when cut along lines AA″ (see FIG. 1B) is shown in FIG. 1F.
FIG. 1B shows a perspective view of a wafer as is seen when cut in the direction of line BB″ shown in FIG. 1A. Referring to FIG. 1A, after the formation of a Si3N4 layer on a Si substrate, the Si3N4 layer is patterned using photoresist (e.g., PR). Subsequently, as shown in FIG. 1C, trenches are etched in the substrate and a layer of SiO2 is formed in the trenches and over the remaining portions of the Si3N4 layer. Next, as shown in FIG. 1D, a CMP operation is performed in order to remove the Si3N4 layer.
A first layer of polysilicon 120 is then deposited on the surface of the remaining material (e.g., see FIG. 1D, TOX layer 122). Subsequently, as is shown in FIG. 1E, an etch of the first polysilicon layer 120 is performed and a layer of ONO 124 thereafter deposited. This is followed by the deposition of a second polysilcon layer 121. Finally, a stacked gate etch is performed resulting in the structure shown in FIG. 1F.
As is shown in FIG. 1F, a stacked gate structure may result from the process outlined in FIGS. 1A–1F. The illustration of FIG. 1F depicts a perspective view of the wafer as seen when cut along lines A″ of FIG. 1A as was mentioned above. The first and second polysilicon layers (e.g., 120 and 121) are vertically aligned with the ONO layer in a stacked gate configuration. A VCI implant 123 is performed to connect all of the sources together. A very heavy VCI implant 123 is needed to form a low resistance line.
Problematic short channel effects result from the heavy VCI implantation 123 needed to form conductive lines that have low resistance. It should be appreciated that the effective channel length (e.g., Leff) of the fabricated device is decreased as a result of the lateral diffusion of the source junction caused by such heavy VCI implantation 123. This lateral diffusion may significantly degrade the performance of the device.